Search Results - "2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)"
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Surface finishing of cleaved SOI films using epi technologies
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…The use of epi technologies in SOI manufacturing is shown to add flexibility and increased wafer quality, e.g. fewer defects and better top Si-layer…”
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Smart card circuits in SOI technology
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Smart cards have recently evolved towards very complex systems-on-a-chip, thereby opening new opportunities and creating new demands on fabrication…”
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Medium-dose SIMOX quality improvement for advanced CMOS applications
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Reducing the oxygen dose for implanted (i.e. SIMOX) SOI material, and improving the implantation equipment and process balance, have been pursued in order to…”
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Non-stationary transport effects: impact on 0.1 /spl mu/m PD SOI technology
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…When devices are scaled-down in the sub-0.1 /spl mu/m domain, the classical drift-diffusion (DD) model fails to predict velocity overshoot and carrier…”
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The drive currents improvement of FDSOI MOSFETs with undoped Si epitaxial channel and elevated source/drain structure
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Fully-depleted silicon-on-insulator (FDSOI) MOSFETs are very attractive for low-voltage applications due to ideal subthreshold slope, short channel effect…”
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Scalability potential in ELTRAN/sup (R)/ SOI-epi wafer
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that…”
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Circuit design in SOI: concept of floating /spl beta/ ratio
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…SOI is becoming a well accepted technology, but for circuit designers, it still has hidden roadblocks and unknown performance gains. To help circuit designers…”
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Impact of the gate-to-body tunneling current on SOI history effect
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…The gate dielectric thickness has been aggressively scaled in recent technology generations. The thin gate dielectric is essential to maintain and improve the…”
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Elimination of square pits on SIMOX wafer by using nitrogen-doped Cz crystal
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Recent developments in LSI technology require SOI wafers for realization of higher speed operation and lower power consumption. SIMOX wafers are one of the…”
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Design guideline and performance prediction of 'SBB' SOI MOSFETs
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Characteristics of 'self-body-biased' ('SBB') SOI MOSFETs (Terauchi and Terada, 1999) have been studied in detail. Static simulations show that both the…”
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A 0.5-1 V MTCMOS/SIMOX SRAM macro with multi-V/sub th/ memory cells
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Summary form only given. Sub-1 V CMOS circuit technology on ultrathin-film SOI is the most effective candidate for ultralow-power applications in future ULSIs…”
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RF systems based on silicon-on-sapphire technology
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…The major issues which confronted the formation of very thin layers of silicon (30-100 nm) on sapphire substrates for application to mm-wave communication and…”
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Extraction of the main current components of floating-body partially-depleted SOI devices
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…CMOS SOI technology is a promising candidate for mixed analog/digital low-voltage/low-power applications due to its low threshold voltage capability…”
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Architecture of SOI transistors: what's next?
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…The long but successful efforts of the silicon-on-insulator (SOI) community have eventually put SOI in the microelectronics roadmap. It is frequently stated…”
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Performance improvements in high-density DRAM application using 0.15 /spl mu/m body-contacted SOI technology
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…A 0.15 /spl mu/m silicon-on-insulator (SOI) CMOS technology, using a body-contacted (BC) SOI structure, is developed. This process technology is fully…”
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An impact of GIDL off leakage on low-power sub-0.2 /spl mu/m SOI CMOS applications
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…The speed advantage of SOI CMOSFETs has exclusively been claimed for front-end applications (Ajmera et al, 1999), but its potential for low-power applications…”
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Preparation of 200 mm silicon substrates with metal ground-plane for double-gate SOI devices
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…As the current CMOS VLSI technology approaching fundamental limits in the deep submicron regime, double-gate SOI devices provide an alternative device…”
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Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in fully-depleted (FD) SOI MOSFETs. In order to suppress this…”
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New planar self-aligned double-gate fully-depleted P-MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D)
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Simulations have shown that self-aligned double-gate SOI MOSFETs are able to eliminate short channel effects and increase circuit performance for devices down…”
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A high-performance body-charge-modulated SOI sense amplifier
Published in 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125) (2000)“…Dynamic CMOS SOI sensing circuits are prone to performance variation and mismatch in transfer characteristics (Kuang et al, 1997; Allen et al, 1999) as a…”
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