Search Results - "1992 Proceedings of the IEEE Custom Integrated Circuits Conference"

1
Computational Ram: A Memory-simd Hybrid And Its Application To Dsp by Elliott, D.G., Snelgrove, W.M., Stumm, M.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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Fault Model Evolution For Diagnosis: Accuracy vs Precision by Acken, J.M., Millman, S.D.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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A Top-down, Constraint-driven Design Methodology For Analog Integrated Circuits by Chang, H., Sangiovanlli-Vincentelli, A., Balarin, F., Charbon, E., Choudhury, U., Jusuf, G., Liu, E., Malavasi, E., Neff, R., Gray, P.R.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer by Ratzlaff, C.L., Pullela, S., Pillage, L.T.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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A Constraint-driven Placement Methodology For Analog Integrated Circuits by Charbon, E., Malavasi, E., Choudhury, U., Casotto, A., Sangiovanni-Vincentelli, A.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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3.3V-5V compatible I/O circuit without thick gate oxide by Takahash, M., Sakurai, T., Sawada, K., Nogami, K., Ichida, M., Matsuda, K.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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Wiring And Crosstalk Avoidance In Multi-chip Module Design by Chen, H.H., Wong, C.K.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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8
Optimization of parametric yield: A tutorial by Director, S.W., Feldmann, P., Krishna, K.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)
“…Yield loss can be characterized as either catastrophic or parametric. Catastrophic yield loss is primarily due to local, or spot, defects that occur in a…”

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A Low Jitter 5 Mhz To 180 Mhz Clock Synthesizer For Video Graphics by Shaiatdoust, R., Nagaraj, K., Saniski, M., PIany, J.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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10
Automatic Analog Model Generation For Behavioral Simulation by Antao, B.A.A., El-Turky, F.M.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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11
Behavioral Representations For VCO And Detectors In Phase-lock Systems by Liu, E., Sangiovanni-Vincentelli, A.L.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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12
Clock Tree Synthesis Based On Rc Delay Balancing by Minami, F., Takano, M.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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13
Clock Buffer Chip With Absolute Delay Regulation Over Process And Environmental Variations by Watson, R.B., Collins, H.A., Iknaian, R.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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14
Optimization Of Channel Segmentation For Channelled Architecture FPGAs by Roy, K., Mehendale, M.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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15
A 1 GBIT/second GaAs DES chip by Eberle, H., Thacker, C.P.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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16
Modeling, Simulation And Optimization Of Analog Macromodels by Ma, V.M., Singh, J., Saleh, R.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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17
Rapid Redesign Of Analog Standard Cells Using Constrained Optimization Techniques by Maulik, P.C., Flynn, M.J., Allstot, D.J., Carley, L.R.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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18
An Ultra-high Speed Public Key Encryption Processor by Ivey, P.A., Walker, S.N., Stern, J.M., Davidson, S.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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19
An MPGA Compatible FPGA Architecture by Marple, D., Cooke, L.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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20
A Cascadable Neural Network Chip Set With On-chip Learning Using Noise And Gain Annealing by Jayakumar, A., Alspector, J.

Published in 1992 Proceedings of the IEEE Custom Integrated Circuits Conference (1992)

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Search Results - "1992 Proceedings of the IEEE Custom Integrated Circuits Conference"

Computational Ram: A Memory-simd Hybrid And Its Application To Dsp by Elliott, D.G., Snelgrove, W.M., Stumm, M.

Fault Model Evolution For Diagnosis: Accuracy vs Precision by Acken, J.M., Millman, S.D.

A Top-down, Constraint-driven Design Methodology For Analog Integrated Circuits by Chang, H., Sangiovanlli-Vincentelli, A., Balarin, F., Charbon, E., Choudhury, U., Jusuf, G., Liu, E., Malavasi, E., Neff, R., Gray, P.R.

Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer by Ratzlaff, C.L., Pullela, S., Pillage, L.T.

A Constraint-driven Placement Methodology For Analog Integrated Circuits by Charbon, E., Malavasi, E., Choudhury, U., Casotto, A., Sangiovanni-Vincentelli, A.

3.3V-5V compatible I/O circuit without thick gate oxide by Takahash, M., Sakurai, T., Sawada, K., Nogami, K., Ichida, M., Matsuda, K.

Wiring And Crosstalk Avoidance In Multi-chip Module Design by Chen, H.H., Wong, C.K.

Optimization of parametric yield: A tutorial by Director, S.W., Feldmann, P., Krishna, K.

A Low Jitter 5 Mhz To 180 Mhz Clock Synthesizer For Video Graphics by Shaiatdoust, R., Nagaraj, K., Saniski, M., PIany, J.

Automatic Analog Model Generation For Behavioral Simulation by Antao, B.A.A., El-Turky, F.M.

Behavioral Representations For VCO And Detectors In Phase-lock Systems by Liu, E., Sangiovanni-Vincentelli, A.L.

Clock Tree Synthesis Based On Rc Delay Balancing by Minami, F., Takano, M.

Clock Buffer Chip With Absolute Delay Regulation Over Process And Environmental Variations by Watson, R.B., Collins, H.A., Iknaian, R.

Optimization Of Channel Segmentation For Channelled Architecture FPGAs by Roy, K., Mehendale, M.

A 1 GBIT/second GaAs DES chip by Eberle, H., Thacker, C.P.

Modeling, Simulation And Optimization Of Analog Macromodels by Ma, V.M., Singh, J., Saleh, R.

Rapid Redesign Of Analog Standard Cells Using Constrained Optimization Techniques by Maulik, P.C., Flynn, M.J., Allstot, D.J., Carley, L.R.

An Ultra-high Speed Public Key Encryption Processor by Ivey, P.A., Walker, S.N., Stern, J.M., Davidson, S.

An MPGA Compatible FPGA Architecture by Marple, D., Cooke, L.

A Cascadable Neural Network Chip Set With On-chip Learning Using Noise And Gain Annealing by Jayakumar, A., Alspector, J.

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