Search Results - "1991 Symposium on VLSI Technology"

A Novel Trench Capacitor Structure for ULSI DRAMs by Rajeevakumar, T.V., Bronner, G.B.

“…The DRAM is rapidly scaling towards the 256 Mb generation. As the surface opening of the storage capacitor is scaled down along with DRAM cell area for high…”
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A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase by Kume, H., Tanaka, T., Adachi, T., Miyamoto, N., Saeki, S., Ohji, Y., Ushiyama, M., Kobayashi, T., Nishida, T., Kawamoto, Y., Seki, K.

“…This paper describes a 3.42 μ m2 memory cell technology for a simple stacked gate Flash Memory, based on a 0.6μ m CMOS process. A sector erase scheme which…”
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High Performance Shallow Junction Well Transistor (SJET) by Mizuno, T., Asao, Y., Koga, J.

“…Recently, several new MOSFET structures have been developed for VLSIs. Especially, low channel depletion layer capacitance structure, such as a thin film SOI…”
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Two step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact-Penetrating Cellplate (SABPEC) for 64MbDRAM STC Cell by Itob, H., Miyagawa, Y., Takahashi, M., Mitsuhashi, T., Kimura, Y., Endoh, A., Nagatomo, Y., Yoshimaru, M., Ichikawa, F., Ino, M.

“…In this paper, the 1.5mum2 STC is reported with Two step Deposited Rugged Surface Poly-Si (TDRS) enabling fin shape storagenode and also with a Self-Aligned…”
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A 0.5/spl mu/m Diode Load 4Mb Sram Technology Using Double-Level Al Plug Metal Process by Sundaresan, R., Wei, C.C., Zamanian, M., Chen, F.S., Miller, R.O., Hodges, R.L., Gaskins, W., Sagarwala, P., Nguyen, L., Huang, J., Spinner, C., Stagaman, G.S., Hata, W., Lin, Y.S., Bryant, F., Liou, F.T.

“…A 4Mb SRAM technology using 0.5 μ m transistors with 12.5 nm gate oxide, TiN local interconnection, polysilicon diode loads, and Al plug double level…”
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Fully SiO/sub 2/ Isolated High Speed Self-Aligned Bipolar Transistor on Thin SOI by Nishizawa, H., Azuma, S., Yoshitake, T., Kawata, S., Ikeda, T., Kawaji, M., Anzai, A.

“…This paper describes the high performance of fully SiO2 isolated self-aligned bipolar transistor SEPT (Selective Etching of Polysilicon Technology) [3] using…”
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An Ultra-High Emitter Efficiency Transistor with a Low-Temperature Processed Polysilicon Emitter for High-Speed Bipolar Ulsis by Kondo, M., Namba, M., Kobayashi, T., Iijima, S., Nakamura, T.

“…In this paper, we present a transistor having a novel polysilicon emitter with an ultra-shallow n+ diffused layer, formed by low-temperature annealing of a…”
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Multilayer Vertical Stacked Capacitors (mvstc) for 64mbit and 256mbit Drams by Temmler, D.

“…As DRAM cell size is being reduced, scaling stacked capacitor structures is becoming more difficult and process extensions to increase the storage area…”
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55 Ghz Polysilicon-Emitter Graded Sige-Base Pnp Transistors by Harame, D.L., Meyerson, B.S., Crabbe, E.F., Stanis, C.L., Cotte, J.M., Stork, J.M.C., Megdanis, A.C., Patton, G.L., Stiffler, S.R., Johnson, J.B., Warnock, J.D., Comfort, J.H., Sun, J.Y.-C.

“…SiGe-Base PNP transistors with dramatically reduced valence band barrier effects on the DC and AC characteristics were fabricated with an N-type UHV/CVD…”
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A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies by Kodama, N., Saitoh, K., Shirai, H., Okazawa, T., Hokari, Y.

“…A highly reliable 5V only 16Mbit Flash EEPROM cell (3.6μm2 cell size, same as an UV EPROM[1]) has been developed. The technologies used were as follows:…”
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Influence of Under-Metal Planes on Al by Shibata, H., Ikeda, N., Murota, M., Asahi, Y., Hashimoto, K.

“…This study focuses on the crystallographic effects of under-metal planes on Al(111) orientation. it has been found that Al(111) preferred orientation is…”
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Flash EEPROM Cell scaling based on tunnel oxide thinning limitations by Yosbikawa, K., Mori, S., Sakagami, E., Arai, N., Kaneko, Y., Ohshima, Y.

“…The paper describes an ETOX cell scaling scenario which considers tunnel oxide scaling limitations. Operation voltages are also derived from this scenario…”
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Submicron Mechanically Planarized Shallow Trench Isolation With Field Shield by Linderiberger, W.S., Kornblit, A., Lai, W., Hillenius, S.J., Chen, M.-L.

“…Submicron transistors and test structures have been fabricated using a mechanically planarized shallow trench isolation scheme which incorporates a poly-Si…”
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Soft Error Immune 180/spl mu/m/sup 2/ Sicos Upward Transistor Memory Cell Suitable for Ultra-High-Speed High-Density Bipolar Memories by Idei, Y., Shiba, T., Homma, N., Yamaguchi, K., Nakamura, T., Onai, T., Namba, M., Tarnaki, Y., Sakurai, Y.

“…This paper describes an improved 180μ m2 SICOS upward transistor memory cell, which is the smallest switched-load-resistor type memory cell in existence. The…”
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A Thin-Base Lateral Bipolar Transistor Fabricated on Bonded SOI by Higaki, N., Fukano, T., Fukuroda, A., Sugii, T., Arimoto, Y., Ito, T.

“…In this paper, we describe a thin-base lateral BJT fabricated on bonded SOI, and explore the device's characteristics. High gain, high-speed AC characteristics…”
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Process Integration for a 2ns Cycle/4ns Access 512K CMOS SRAM by Joshi, R., Klepner, S., Basavaiah, S., Ray, A., Petrillo, K., Mazzeo, N., Bucelot, T., Brodsky, S., Jaso, M., Brunner, T., Petrillo, E., Stein, K., Lii, T., Franch, R., Chappell, B., Chappell, T., Schuster, S.

“…Recent results for a 512Kb SRAM [1] demonstrated a 2ns cycle and 4ns access performance. Essential to achieving this high speed result was optimization of the…”
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0.25/spl mu/m Contact Hole Filling by Al-Ge Reflow Sputtering by Kikuta, K., Kikkawa, T., Aoki, H.

“…This paper reports submicron-contact-hole filling by Al-Ge reflow sputtering. it was conducted using a conventional DC magnetron sputter system without any…”
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A 26ps Selective Epitaxial Bipolar Technology by Meister, T.F., Meul, H.W., Stengl, R., Hartwig, D., Weyl, R., Kerner, I., Mahnkopf, R., Schreiter, R., Weng, J., Kopl, R.

“…A high performance, selfaligned bipolar transistor has been developed by using the SEG (Selective Epitaxial Growth) - technology. Key features of the…”
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Gate-Induced Drain Leakage in Ldd and Fully-Overlapped Ldd Mosfets by Parke, S., Moon, J., Nee, P., Huang, J., Hu, C., Ko, P.K.

“…Gate-Induced Drain Leakage (GIDL), caused by band-to-band tunneling in the gate-overlap region of the drain, has been shown to impose a major constraint on the…”
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Laterally-Doped Channel(LDC) Structure for Sub-Quarter Micron MOSFETs by Matsuki, T., Asakura, F., Saitoh, S., Matsumoto, H., Fukuma, M., Kawamura, N.

“…Hot carrier generation, short channel effect and current drivability degradation are major problems for designing "sub-quarter micron" MOSFECTs. LDD structures…”
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