Search Results - "1989 Proceedings of the IEEE Custom Integrated Circuits Conference"

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  1. 1

    Extending SPICE for electro-thermal simulation by Vogelsong, R.S., Brzezinski, C.

    “…A discussion is presented of modifications to the SPICE program that allow the simultaneous simulation of an electrical system and a thermal network. By…”
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    Conference Proceeding
  2. 2

    The effect of logic block complexity on area of programmable gate arrays by Rose, J., Francis, R.J., Chow, P., Lewis, D.

    “…The authors explore the tradeoff between the area of a programmable gate array (PGA) and the functionality of its logic block. A set of industrial circuits is…”
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  3. 3

    A self-testing ALU using built-in current sensing by Nigh, P., Maly, W.

    “…A CMOS ALU (arithmetic logic unit) chip containing built-in current (BIC) sensors, which perform self-testing of the ALU, is described. The performance of two…”
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  4. 4

    Detecting stuck-open faults with stuck-at test sets by Millman, S.D., McCluskey, E.J.

    “…Simulations of CMOS combinational circuits have been conducted to determine the relationship between stuck-at and stuck-open fault coverage. The results…”
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  5. 5

    BiNMOS: a basic cell for BiCMOS sea-of-gates by El Gamal, A., Kouloheris, J.L., How, D., Morf, M.

    “…A BiNMOS test chip has been designed and fabricated in 0.8-μm BiCMOS technology. The test chip consists of a 4×22 array of BiNMOS cells. The test structures…”
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  6. 6

    A four chip implantable defibrillator/pacemaker chipset by Ryan, J.G., Carroll, K.J., Pless, B.D.

    “…A system of four integrated circuits along with discretes that form part of an implantable defibrillator is outlined. Circuit techniques to reduce battery…”
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  7. 7

    A monolithic 50-200 MHz CMOS clock recovery and retiming circuit by Baumert, R.J., Metz, P.C., Pedersen, M.E., Pritchett, R.L., Young, J.A.

    “…A single-chip realization of a clock recovery and data retiming circuit is described. The circuit has been manufactured in a 0.9-μm digital CMOS technology and…”
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  8. 8

    ACACIA: the CMU analog design system by Carley, L.R., Garrod, D., Harjani, R., Kelly, J., Lim, T., Ochotta, E., Rutenbar, R.A.

    “…A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS,…”
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  9. 9

    A serial interfacing technique for built-in and external testing of embedded memories by Nadeau-Dostie, B., Silburt, A., Agarwal, V.K.

    “…A description is presented of a serial interfacing technique for embedded RAMs, which has been successfully applied to static single-port and dual-port…”
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  10. 10

    Built-in self-repair circuit for high-density ASMIC by Sawada, K., Sakurai, T., Uchino, Y., Yamada, K.

    “…A built-in self-repair (BISR) circuit is introduced to achieve high yield and to overcome the testing problem for high-density application-specific memory ICs…”
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  11. 11

    A programmable 1400 MOPS video signal processor by Huizer, C.M., Baker, K., Mehtani, K., De Block, J., Dijkstra, H., Hynes, P.J., Lammerts, J.A.M., Lecoutere, M.M., Popp, A., van Roermund, A.H.M., Sheridan, P., Sluyter, R.J., Welten, F.P.J.M.

    “…A description is given of a digital, general-purpose, programmable IC especially designed for flexible processing of video signals. The IC is implemented in a…”
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  12. 12

    Limitations of the stuck-at fault model as an accurate measure of CMOS IC quality and a proposed schematic level fault model by Lipp, R.J.

    “…Limitations in current testability approaches have forced major compromises in IC fault modeling, test, and quality. The stuck-at fault model is inadequate to…”
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  13. 13

    A high speed data encryption processor for public key cryptography by Rosati, T.

    “…A cost-effective public key cryptographic architecture and its implementation in 2-μm double-level-metal CMOS are presented. The latter consists of a 593-bit…”
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  14. 14

    A 5000-gate CMOS EPLD with multiple logic and interconnect arrays by Wong, S.C., So, H.C., Ou, J.H., Costello, J.

    “…A description is given of a CMOS electrically programmable logic device (EPLD) with over 220000 programmable elements organized into multiple logic array…”
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  15. 15

    Operational amplifier compilation with performance optimization by Onodera, H., Kanbara, H., Tamaru, K.

    “…A design methodology is described for analog circuits in which topological design is followed by simultaneous device sizing and layout design. By merging…”
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  16. 16

    Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits by George, P., Ko, P.K., Hu, C.

    “…A device model is described for the simulation of the effects of single-event and radiation phenomena on the operation of GaAs MESFETs. The model can be…”
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  17. 17

    Design and optimisation of CMOS wideband amplifiers by Op't Eynde, F., Sansen, W.

    “…Several CMOS amplifier types are compared and optimized for high-frequency applications. Scaling laws are derived for the power consumption as a function of…”
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  18. 18

    An 8-bit two-step flash A/D converter for video applications by Cremonesi, A., Maloberti, F., Torelli, G., Vacchi, C.

    “…A novel configuration for two-step analog-to-digital (A/D) flash conversion is described. The coarse and fine conversions are performed with a four-bit…”
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  19. 19

    A high speed FIR filter designed by compiler by Hartley, R., Corbett, P., Jacob, P., Karr, S.

    “…Digital-serial computation is a hybrid between bit-serial computation and parallel computation. In digit-serial computation, data is divided into digits of N…”
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  20. 20

    Design automation system for analog circuits based on fuzzy logic by Hashizume, M., Kawai, H.Y., Nii, K., Tamesada, T.

    “…A design automation algorithm is proposed, and its effectiveness is evaluated by a prototype system. The goal is to obtain the near-optimum parameters for…”
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