Search Results - "1972 IEEE 2nd Symposium on Computer Arithmetic (ARITH)"

Refine Results
  1. 1

    A negative-binary adder-subtracter by Rao, G. S., Krishnamurthy, A. V., Rao, M. N.

    “…The logical design of an adder-subtracter for negative binary numbers is described. The twin-carry generates during the addition, is converted into a single…”
    Get full text
    Conference Proceeding
  2. 2

    A polarizer for negative binary numbers by Rao, G. S., Krishnamurthy, E. V., Rao, M. N.

    “…The logical design of a polarizer for negative binary numbers is described and compared with the two's complementer used for positive binary numbers…”
    Get full text
    Conference Proceeding
  3. 3

    Eadix l6 evaluation of some elementary functions by Ercegovac, M. D.

    “…This paper describes an approach for obtaining a class of similar algorithms for evaluation of some elementary functions. The main objective is to show…”
    Get full text
    Conference Proceeding
  4. 4

    Analyzed binary computing by Metropolis, N.

    “…A single format for the representation of numbers in a computer is proposed to accommodate both exact and inexact quantities. A consistent set of rules is…”
    Get full text
    Conference Proceeding
  5. 5

    Paper not submitted

    “…The document was not made available for publication as part of the conference proceedings…”
    Get full text
    Conference Proceeding
  6. 6

    A simulative study of correlated error propagation in various finite arithmetics by Marasa, J. D., Matula, D. W.

    “…The accumulated round-off error incurred in long arithmetic computations involving a randomized mixture of addition, subtraction, multiplication and division…”
    Get full text
    Conference Proceeding
  7. 7

    Analog techniques for residue operations by Cauthen, T. L., Rao, T. R.

    “…The precision required for residue operations is primarily associated with resistive components and operational amplifiers. However, technology has advanced to…”
    Get full text
    Conference Proceeding
  8. 8

    Foundations of finite precision arithmetic by Matula, D. M.

    “…Completeness and uniqueness properties for the representation of the base β digital numbers by finite length radix polynomials with various digit sets are…”
    Get full text
    Conference Proceeding
  9. 9

    Multiresidue codes for double error correction by Monteiro, P., Rao, T. R. N.

    “…A new class of (separate) multiresidue codes has been proposed, which is capable of double error correction. The codes are derived from a class of AN codes…”
    Get full text
    Conference Proceeding
  10. 10

    Changing from the Arabic-decimal system to the "Assembler Digit-Base-16" system by Whitaker, R. O.

    “…About the time that Athens and Sparta were destroying each other, the Romans developed a numbering system which was to be used by the entire civilized world…”
    Get full text
    Conference Proceeding
  11. 11

    Error correction in redundant residue number systems by Yau, S. S., Liu, Y. C.

    “…In this paper, two error-correcting algorithms for redundant residue number systems are presented, one for single residue-error correction and the other for…”
    Get full text
    Conference Proceeding
  12. 12

    Pipelining of arithmetic functions by Hallin, T. G., Flynn, M. J.

    “…Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency. A definition of efficiency was derived to…”
    Get full text
    Conference Proceeding
  13. 13

    Groupoids and computer arithmetic by Garner, H. L., Foo, N., Lo Hsieh

    “…Overflow detection and overflow recovery imposed no particular requirements on the structure of (X, X 1 <; X 1 , f x ). In particular, if f is associative and…”
    Get full text
    Conference Proceeding
  14. 14

    Considerations in the design of a high speed decimal unit by Schmookler, M. S.

    “…New applications and new technologies will make high speed decimal arithmetic an attractive alternative to binary arithmetic. This new environment will be…”
    Get full text
    Conference Proceeding
  15. 15

    Parallel processing in Boolean algebra by Svoboda, A.

    “…A processor called Boolean Analyzer has been presented at IFIP Congress 1968 to introduce parallel processing of Boolean expressions [1]. The present paper…”
    Get full text
    Conference Proceeding
  16. 16

    Standards for computer arithmetic by Marcovitz, A. B.

    “…A set of standards for the design of the arithmetic unit of all general purpose digital computers has been proposed. This paper discusses that proposal and…”
    Get full text
    Conference Proceeding
  17. 17

    The analysis and design of a class of quotient digit selectors by Atkins, D. E.

    “…The work to date has provided analytic tools to help answer design questions about table look-up type quotient selectors, and also a means for computer-aided…”
    Get full text
    Conference Proceeding
  18. 18

    Roundings in floating point arithmetic by Yohe, J. M.

    “…In this paper we discuss directed roundings and indicate how hardware might be designed to produce proper upward-directed, downward-directed, and certain…”
    Get full text
    Conference Proceeding
  19. 19

    On the precision attainable with various floating-point number systems by Brent, R. P.

    “…For scientific computations on a digital computer the set of real numbers is usually approximated by a finite set F of "floating-point numbers". We compare the…”
    Get full text
    Conference Proceeding
  20. 20

    The status of investigations into the use of continued fractions for computer hardware by Robertson, J. E., Trivedi, K.

    “…The purpose of this paper is to demonstrate that representations of numbers other than positional notation may lead to practical hardware realizations for the…”
    Get full text
    Conference Proceeding