Search Results - "13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)"

Efficient hardware data mining with the Apriori algorithm on FPGAs by Baker, Z.K., Prasanna, V.K.

“…The Apriori algorithm is a popular correlation-based data mining kernel. However, it is a computationally expensive algorithm and the running times can stretch…”
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An execution environment for reconfigurable computing by Fu, W., Compton, K.

“…Although many studies have demonstrated the benefits of reconfigurable computing, it has not yet penetrated the mainstream. One of the biggest unsolved…”
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Terrestrial-based radiation upsets: a cautionary tale by Quinn, H., Graham, P.

“…Problems with terrestrial-based neutron radiation from cosmic rays have become more commonplace. While the incident rate from neutron radiation is lower than…”
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Fast reconfiguring deep packet filter for 1+ gigabit network by Cho, Y.H., Mangione-Smith, W.H.

“…Due to increasing number of network worms and virus, many computer network users are vulnerable to attacks. Unless network security systems use more advanced…”
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A comparison of floating point and logarithmic number systems for FPGAs by Haselman, M., Beauchamp, M., Wood, A., Hauck, S., Underwood, K., Hemmert, K.S.

“…There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and…”
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An analysis of the double-precision floating-point FFT on FPGAs by Hemmert, K.S., Underwood, K.D.

“…Advances in FPGA technology have led to dramatic improvements in double precision floating-point performance. Modern FPGAs boast several GigaFLOPs of raw…”
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The Erlangen Slot Machine: a highly flexible FPGA-based reconfigurable platform by Bobda, C., Majer, M., Ahmadinia, A., Haller, T., Linarth, A., Teich, J.

“…We present a new concept as well as the implementation of an FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). The main advantages of this…”
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An open TCP/IP core for reconfigurable logic by Dollas, A., Ermis, I., Koidis, I., Zisis, I., Kachris, C.

“…This project is aimed at developing the full TCP/IP protocol as an open-source IP core which can be freely used, as well as to develop know-how on protocol…”
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A framework for rule processing in reconfigurable network systems by Attig, M., Lockwood, J.

“…High-performance rule processing systems are needed by network administrators in order to protect Internet systems from attack. Researchers have been working…”
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A novel 2D filter design methodology for heterogeneous devices by Bouganis, C.-S., Constantinides, G.A., Cheung, P.Y.K.

“…In many image processing applications, fast convolution of an image with a large 2D filter is required. Field programable gate arrays (FPGAs) are often used to…”
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Metropolitan road traffic simulation on FPGAs by Tripp, J.L., Mortveit, H.S., Hansson, A.A., Gokhale, M.

“…This work demonstrates that road traffic simulation of entire metropolitan areas is possible with reconfigurable supercomputing that combines 64-bit…”
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Register file architecture optimization in a coarse-grained reconfigurable architecture by Kwok, Z., Wilton, S.J.E.

“…This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture. The register…”
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A high-performance asynchronous FPGA: test results by Fang, D., Teifel, J., Rajit Manohar

“…We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC's 0.18 /spl mu/m CMOS process. The AFPGA uses SRAM-based configuration…”
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Time domain numerical simulation for transient waves on reconfigurable coprocessor platform by He, C., Zhao, W., Lu, M.

“…A successful application-oriented reconfigurable coprocessor design requires not only a powerful FPGA-based computing engine along with suitable hardware…”
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Higher radix floating-point representations for FPGA-based arithmetic by Catanzaro, B., Nelson, B.

“…FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations. The general computing world…”
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A signature match processor architecture for network intrusion detection by Janardhan Singaraju, Bu, L., Chandy, J.A.

“…In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the…”
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A study of the scalability of on-chip routing for just-in-time FPGA compilation by Lysecky, R., Vahid, F., Tan, S.D.-X.

“…Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor…”
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High-performance FPGA-based general reduction methods by Morris, G.R., Zhuo, L., Prasanna, V.K.

“…FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose…”
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Simplifying the integration of processing elements in computing systems using a programmable controller by Shannon, L., Chow, P.

“…As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new…”
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Hardware factorization based on elliptic curve method by Simka, M., Pelzl, J., Kleinjung, T., Franke, J., Priplata, C., Stahlke, C., Drutarovsky, M., Fischer, V., Paar, C.

“…The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for…”
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